This invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a dielectrically isolated semiconductor integrated circuit device having semiconductor regions having different conductivity types on the same substrate.
In the manufacture of semiconductor circuit devices it is often necessary to form semiconductor elements having different conductivity types on the same semiconductor chip.
For example, where PNP and NPN bipolar transistors isolated by a PN junction are to be formed on a P type semiconductor substrate, in order to prevent increase in the number of manufacturing steps, usually the PNP transistor would have a lateral construction. Such a PNP transistor having a lateral construction generally has such inferior electric characteristics as the current gain, high frequency characteristics to an NPP transistor having a vertical construction so that it is not suitable to combine the PNP transistor with an NPN transistor to form a complementary circuit.
To form PNP and NPN transistors having excellent electrical characteristics on the same substrate, a semiconductor substrate provided with island regions having different conductivity types and isolated by an insulator has been used.
FIGS. 1a through 1f show successive steps of manufacturing a prior art dielectrically isolated semiconductor integrated circuit device.
In the step shown in FIG. 1a, the surface of a P type single-crystal silicon substrate 1 having a crystalline surface &lt;100&gt; is anisotropically etched to form a recess 9 by using a selective mask 2. Then, as shown in FIG. 1b, a silicon layer 3 having substantially the same thickness as the depth of the recess 9 is epitaxially grown on the surface of the silicon substrate 1. Since the mask 2 is not single-crystal a polycrystalline silicon layer 4 would be formed on the surface of the mask 2. Then, as shown in FIG. 1c, the epitaxially grown layer 3 and the polycrystalline silicon layer 4 are removed by mechanical grinding. After removing the mask 2, the substrate is subjected twice to photolithographic steps to form by diffusion a high concentration diffused regions 6 on a selected surface portion on the substrate 1 and a high concentration diffused region 7 on a selected surface portion of the epitaxially grown layer 3. Then, as shown in FIG. 1d, the epitaxially grown layer 3 is selectively and anisotropically etched off to form a V-shaped groove 10. Then, as shown in FIG. 1e, a silicon oxide film 5 is thermally grown on the entire surface of the substrate 1, and thereafter a polycrystalline silicon layer 8 acting as a supporting substrate is formed on the entire surface of the silicon oxide film 5. Then, as shown in FIG. 1f, the single-crystal silicon layer is removed from the rear side of the substrate 1 until the oxide film 5 is exposed to form a dielectrically isolated substrate having island regions of different conductivity types.
However, the method described above has the following defects.
More particularly, when forming an epitaxially grown layer on a silicon substrate, since a polycrystalline layer is simultaneously formed, the grown surface of the silicon wafer (silicon substrate) becomes concave. This phenomenon is considered to be caused by the fact that the single-crystal silicon and the polycrystalline silicon have different physical characteristics. Especially when the thickness of the epitaxially grown layer exceeds 30 microns, the warping of the wafer becomes remarkable. Since such warping of the wafer results in a strain in the crystalline structure of the silicon, the strain degrades the electric characteristics of a bipolar transistor element, particularly the current amplification factor and the noise characteristic in a low current region. Moreover, the warping of the wafer causes nonuniform the temperature distribution in the wafer which results in a nonuniformity of the thickness of the epitaxially grown film and growth of a unnecessary epitaxially grown layer or a polycrystalline silicon layer on the rear surface of the wafer.
The method of manufacturing a dielectrically isolated substrate is generally complicated, and the mechanical grinding step performed subsequent to the epitaxially growing step increases the cost of manufacturing. An etching process may be substituted for the grinding step, but as the etching rates of the epitaxially grown layer and the polycrystalline layer are not the same, it is impossible to obtain a flat surface. Moreover, as high impurity regions are formed in the surfaces of the silicon substrate and the epitaxially grown layer, two photolithographic steps are necessary which increases the number of manufacturing steps.